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Using Predefined Types

The cc, CC, and as compiler drivers produce predefined macros listed in Table 7-2. These macros are used in sys/asm.h, sys/regdef.h, and sys/fpregdef.h.

Predefined Macros
32-Bit Executables64-Bit Executables
-D_MIPS_FPSET=16-D_MIPS_FPSET=32
-D_MIPS_ISA=_MIPS_ISA_MIPS1-D_MIPS_ISA=_MIPS_ISA_MIPS3
-D_MIPS_SIM=_MIPS_SIM_ABI32-D_MIPS_SIM=_MIPS_SIM_ABI64
-D_MIPS_SZINT=32-D_MIPS_SZINT=32
-D_MIPS_SZLONG=32-D_MIPS_SZLONG=64
-D_MIPS_SZPTR=32-D_MIPS_SZPTR=64

_MIPS_FPSET describes the number of floating point registers. The 64-bit compilation mode makes use of the extended floating point registers available on the R4000 and R8000 processors.

MIPS_ISA determines the MIPS Instruction Set Architecture. MIPS_ISA_MIPS1 and MIPS_ISA_MIPS3 are the defaults for 32 bits and 64 bits, respectively. For example:

/* Define a parameter for the integer register size: */
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
#define SZREG           4
#else
#define SZREG           8
#endif
MIPS_SIM determines the MIPS Subprogram Interface Model, which describes the subroutine linkage convention and register naming/usage convention.

_MIPS_SZINT, _MIPS_SZLONG, and _MIPS_SZPTR define the size of types int, long, and pointer, respectively.

The 64-bit MIPSpro compiler drivers generate 64-bit pointers and longs and 32-bit ints. Therefore, assembler code that uses either pointer or long types must be converted to use double-word instructions for MIPS III code(-64), and must continue to use word instructions for MIPS I and MIPS II code (-32).

Also, new subroutine linkage conventions and register naming conventions exist. The compiler predefined macro _MIPS_SIM enables macros in sys/asm.h and sys/regdef.h.

Eight argument registers exist: $4 through $11. Four additional argument registers replace the temp registers in sys/regdef.h. These temp registers are not lost, however, as the argument registers can serve also as scratch registers, with certain constraints.

In the _MIPS_SIM_ABI64 model, registers t4 through t7 are not available, so any code using these registers does not compile. Similarly, registers a4 through a7 are not available under the _MIPS_SIM_ABI32 model.

If you are converting assembler code, the new registers ta0, ta1, ta2, and ta3 are available under both _MIPS_SIM models. These alias with registers t4 through t7 in 32-bit mode, and with registers a4 through a7 in 64-bit mode.

Note that the caller no longer has to reserve space for a called function in which to store its arguments. The called routine allocates space for storing its arguments on its own stack, if desired. The NARGSAVE macro in sys/asm.h facilitates this.


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